Use of a C-Element in Chains of Two-Phase CMOS Inverters to Block Noise Pulses Induced by Single Ionizing Particles
https://doi.org/10.1134/S2304487X20020133
Abstract
The TCAD simulation of noise pulses caused by the action of single ionizing particles on the elements of a chain of two-phase CMOS inverters with a C-element on a two-input inverter with the third state has been reported. A noise pulse on one of the inputs of the C-element is blocked, and the C-element stores the last output logical state on the capacitor of the output. The elements are modeled using the 65-nm CMOS bulk technology. Transient processes accompanying the collection of charge from tracks directed along the normal to the crystal surface, with the input points both in the drain area of transistors and at a distance of 0.3–0.65 μm from them have been analyzed. In the case of a track passing through a transistor drain or nearby, interference occurs only on one output of a two-phase inverter and can affect only one input of the next inverter or C-element. The C-element transits to a highly resistive state at the output to store its logical state regardless of the completion of transients in the inverter circuit. The duration of storage is 10–20 ns. The C-element switching delay is 25–40 ps.
Keywords
About the Authors
V. Ya. SteninRussian Federation
115409
117218
Moscow
Yu. V. Katunin
Russian Federation
117218
Moscow
References
1. Muller D. E., Bartky W. S. A theory of asynchronous circuits // Proceedings of International Symposium on the theory of switching, Cambridg, M. A.: Harvard Univ. Press, 1959. P. 204–243.
2. Baker R. J. CMOS circuit design, layout, and simulation (IEEE Press Series on Microelectronic Systems). – Hoboken, New Jersey: John Wiley & Sons, Inc., 2010. P. 351.
3. Hao P., Chen S., Huang P., Chen J., Liang B. A novel SET mitigation technique for clock distribution networks // IEEE Transactions on Device and Materials Reliability. 2018. V. 18. P. 1–8.
4. Ramamurthy C., Gujja A., Vashishtha V., Chellappa S., Clark L.T. Muller C-element self-corrected triple modular redundant logic with multithreading and low power modes // in IEEE Xplore (Conference Section, RADECS-2017), e-book, 2019. P. 184–187.
5. Katunin Yu. V., Stenin V. Ya. Noise immunity of a 28-nm two-phase CMOS combinational logic to transient effects of single nuclear particles // Russian Microelectronics. 2015. V. 44. № 4. P. 255–262.
6. Stenin V. Ya., Katunin Yu. V. Modelirovanie impul’snyh pomekh v dvuhfaznyh KMOP invertorah pri sbore zaryada s treka ioniziruyushchej chasticy (Simulation of noise pulses in two-phase CMOS inverters when collecting charge from an ionizing particle track) // Vestnik NIYaU MIFI, 2019, vol. 8, no. 3, pp. 274–282.
7. Garg R., Khatri S. P. Analysis and design of resilient VLSI circuits: mitigating soft errors and process variations. New York: Springer, 2010. P. 194–205.
8. Soft errors in modern electronic systems / Editor M. Nicolaidis. New York: Springer, 2011. P. 35–37.
Review
For citations:
Stenin V.Ya., Katunin Yu.V. Use of a C-Element in Chains of Two-Phase CMOS Inverters to Block Noise Pulses Induced by Single Ionizing Particles. Vestnik natsional'nogo issledovatel'skogo yadernogo universiteta "MIFI". 2020;9(2):166-176. (In Russ.) https://doi.org/10.1134/S2304487X20020133