The Noise Pulse Compensation in the Ternary CMOS Majority Element on NAND Logical Elements under Impacts of Single Ionizing Particles
https://doi.org/10.1134/S2304487X19040060
Abstract
A CMOS ternary majority element of 65 nm bulk technology has been simulated with measures to improve the resistance to noise pulses arising under the influence of single ionizing particles. The impact on the transistors of the element has been modeled with TCAD tools in the form of the collection of the charge from the track of the particle. Charge collection from tracks with normal direction to the crystal surface is simulated. The linear energy transfer to the track is 60 MeV cm2/mg. The CMOS ternary majority element based only on NAND logical elements has been studied. Its topology is based on the interleaving transistors of the cascade connection of NAND logical elements, which provides increased noise immunity to the impacts of single particles. This ternary majority element has fewer transistors than the standard elements based on AND and OR logical gates. It can be useful to design the majority logic of the elements of 28–65 nm CMOS bulk systems that are resistant to the effects of single nuclear particles.
Keywords
About the Authors
Yu. V. KatuninRussian Federation
117218
Moscow
V. Ya. Stenin
Russian Federation
117218
115409
Moscow
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Review
For citations:
Katunin Yu.V., Stenin V.Ya. The Noise Pulse Compensation in the Ternary CMOS Majority Element on NAND Logical Elements under Impacts of Single Ionizing Particles. Vestnik natsional'nogo issledovatel'skogo yadernogo universiteta "MIFI". 2019;8(4):342-349. (In Russ.) https://doi.org/10.1134/S2304487X19040060